2026/03/06
Enhancement-mode GaN HEMTs feature fast switching speed, low on-resistance, and high power density, and are widely used in high-frequency, high-efficiency power conversion and RF circuits. However, due to their small gate capacitance, low gate threshold voltage (typically between 1V and 2V), and limited voltage tolerance (usually -5V to 7V), special attention must be paid to gate driver design to prevent device failure caused by unintended turn-on or oscillation during switching.
To address this challenge, this article provides an in-depth analysis of the oscillation mechanisms in GaN HEMTs during turn-on and turn-off, and demonstrates how strategies such as proper gate resistance configuration and the addition of an RC damping network between gate and source can effectively suppress oscillations and overshoot. Application testing using the NOVOSENSE NSD2622N high-voltage half-bridge GaN HEMT driver further validates the optimization results under various device and parameter combinations, enabling stable and reliable high-frequency driver designs.
1. Oscillation Mechanisms and Driver Design Considerations in GaN HEMT Switching
Figure 1 GaN HEMT Driver Circuit
A typical GaN HEMT driver circuit is shown in Figure 1, where resistors R1 and R2 adjust the turn-on and turn-off speeds, respectively. The driver loop can be regarded as a series LRC circuit. During turn-on, the gate voltage may exhibit oscillations or overshoots due to the high drain dv/dt and the Miller capacitance (CGD), with the current path illustrated as ISRC in Figure 1. Such oscillations or overshoots can increase GaN HEMT power loss or cause device failure. To avoid excessive oscillation or overshoot, the total equivalent gate resistance during turn-on is recommended to be greater than or equal to the value given in Equation (1):
(1)
Where: LG is the total equivalent parasitic inductance during turn-on; RG(eq) is the total equivalent gate resistance during turn-on; CGS is the equivalent gate capacitance of the GaN HEMT.
During turn-off, the gate voltage may experience negative overshoot or oscillation due to parasitic inductance in the driver loop and the gate turn-off speed. Excessive negative overshoot or oscillation may cause gate breakdown or false turn-on, with the current path shown as Isink in Figure 1. Special attention should be paid during design to avoid excessive negative overshoot or false turn-on.
As can be observed in Figure 1, the current paths ISRC (turn-on) and Isink (turn-off) differ, resulting in different total equivalent parasitic inductances LG and equivalent resistances RG(eq). Specifically, during turn-on, LG includes parasitic inductance from the power supply path, whereas during turn-off, LG does not. This distinction must be considered during analysis and calculation.To better understand the influence of different gate drive resistors on GaN HEMTs, validation tests are conducted using the NSD2622N dual-channel half-bridge GaN HEMT driver from NOVOSENSE with different GaN HEMTs. The tested devices and corresponding results are briefly described below.
2. NOVOSENSE NSD2622N High-Voltage Half-Bridge GaN HEMT Driver
NOVOSENSE NSD2622N is a high-voltage half-bridge GaN HEMT driver in a QFN 5x7 package. Its functional block diagram and pin definitions are shown in Figure 2 and Figure 3, respectively. The device adopts mature capacitive isolation technology, meeting the requirements of high-voltage applications. Both high-side and low-side drivers integrate dedicated positive/negative voltage regulators to provide adjustable positive voltage from 5V-6.5V and fixed negative voltage of -2.5V, ensuring reliable negative-voltage turn-off for GaN HEMTs. The driver features low propagation delay and high drive current (peak source/sink currents of 2A/-4A), satisfying the requirements of diverse systems. It also provides undervoltage lockout (UVLO), over-temperature protection, and dead-time interlock capabilities. It should be noted that the dead-time interlock function can effectively prevent shoot-through in bridge-leg configurations. Additionally, the driver provides a 5V LDO output, offering greater system design flexibility.
Figure 2 NSD2622N Functional Block Diagram Figure 3 NSD2622N Pin Definitions
3. GaN HEMT Parameters
Two high-voltage GaN HEMTs in TOLL packages with Kelvin source pins were used in the validation tests: INNO65TA080BS and GS0650306LL. Their key parameters are listed in the table below.
4. Experimental Results
Figure 4 Double-Pulse Test Setup
A double-pulse test setup, as shown in Figure 4, was used to measure gate waveforms of the GaN HEMTs under different gate resistances. The drive loop reference ground of NSD2622N was connected to the GaN HEMT Kelvin source pin. The total parasitic inductance of the gate drive loop during turn-on was approximately 38nH. Using the CISS value from the GaN HEMT datasheet, the equivalent gate resistance RG(eq) during turn-on should be no less than 26Ω. To directly observe the effects of underdamping, R1 values of 10Ω and 27Ω were tested. The measured waveforms are shown in Table 1, where the blue trace represents the GaN HEMT drain voltage, green represents inductor LM current, and yellow represents GaN HEMT gate voltage.
Table 1 Turn-On Waveforms Before Parameter Adjustment
As shown in Table 1, when R1 = 10Ω, the turn-on drive loop operates in an underdamped mode. At a bus voltage of around 50V, both GaN HEMTs exhibit high-frequency oscillations in gate and drain voltages, rendering the system inoperable. When R1 = 27Ω, both GaN HEMTs operate normally at 400V, but INNO65TA080BS exhibits severe high-frequency oscillation in gate voltage during turn-on. This primarily results from the differences in parasitic inductance of the internal source and di/dt during turn-on between the two GaN HEMTs, leading to distinct gate ringing characteristics. To mitigate such oscillations, R1 was further increased to 33Ω, or an RC snubber (20Ω + 1nF) was added in parallel between the gate and source. These methods reduced the turn-on speed of GaN HEMTs and di/dt during turn-on. The corresponding turn-on and turn-off waveforms are shown in Tables 2 and 3.
Table 2 Turn-On Waveforms After Parameter Adjustment
Table 3 Gate Waveforms During Turn-Off
As shown in Table 2, at a 400V bus voltage, both adjustment methods enable normal operation, with significantly improved gate voltage oscillation and overshoot. Compared with simply increasing R1, connecting an RC snubber in parallel between the gate and source results in a smoother gate voltage without obvious overshoot, but with longer turn-on delay and increased power dissipation. This should be taken into consideration during design.
It can be observed from Table 3 that during negative-voltage turn-off, significant negative overshoot and oscillation occurred at the gate, but no false turn-on was observed. When the RC snubber is absent, the negative overshoot exceeded -5V. After adding the RC snubber, the amplitude of negative overshoot was clearly reduced. The negative overshoot and oscillation during turn-off can be further optimized by adjusting the value of resistor R2 or the RC snubber parameters.
Test results confirm that proper gate drive resistance ensures stable and reliable operation of GaN HEMTs. Excessively small gate resistance can easily cause gate voltage oscillation, potentially leading to system malfunction or failure. Therefore, for enhancement-mode GaN HEMT driver design, the gate drive resistance should ideally satisfy:
This helps prevent gate-source voltage overshoot and oscillation during turn-on. When calculating LG, parasitic inductances from both PCB traces and the chip in the driver loop should be taken into full consideration. For different GaN HEMTs, an appropriate RC snubber can be connected in parallel between the gate and source to effectively suppress oscillation spikes during switching. For high-voltage GaN HEMTs, negative-voltage turn-off can prevent unintended turn-on during turn-off. Additionally, the driver ICs should be placed as close as possible to the GaN HEMT to minimize parasitic inductance in the driver loop, and GaN HEMTs with Kelvin source pins are recommended.
Samples of the NSD2622N series are now available upon request.. Please scan the QR code above and complete the questionnaire to request samples. For further inquiries, contact sales@novosns.com. More product information and technical data are available at www.novosns.com.
